As miniaturization of elements of integrated circuits drives the semiconductor fabrication industry, critical dimensions of elements must be minimized. Further, vertical variation of elements, or “topography”, must be minimized in order to increase lithography and etch process windows and, ultimately, the yield of integrated circuits.
Conventional shallow trench isolation (STI) fabrication techniques include forming a planarization stop layer, e.g., silicon nitride, on an upper surface of a semiconductor substrate, etching the planarization stop layer and semiconductor substrate to form a trench in the semiconductor substrate, forming a thermal oxide liner in the trench, and overfilling the trench with isolation material, such as silicon oxide, to form an overburden on the nitride planarization stop layer. Planarization is then implemented, such as by conducting chemical mechanical polishing (CMP). During subsequent processing, the planarization stop layer is removed followed by formation of active areas for semiconductor devices, which typically involve masking, ion implantation, and cleaning steps.
Different types of semiconductor devices formed in an integrated circuit may require different heights of underlying insulator material, such as oxide. For example, in forming field-effect transistor (FET) devices, an insulator is present between a gate electrode and a semiconductor substrate. Different types of FET devices are functionally optimized with different thicknesses of gate insulator that must be formed on a semiconductor substrate during processing. The thickness of the gate insulation, also referred to as the gate oxide, affects several properties of the resulting transistor. As such, FET devices having several different gate thicknesses are increasingly required for modern semiconductor devices. For example, various FET devices such as thin gate oxide FET devices, medium thick gate oxide FET devices, and thick gate oxide FET devices all require different gate oxide thickness for optimal performance.
Masking, photolithography patterning, and etching processes are employed to form each insulation thickness that is required for each type of FET device to be formed. STI regions that are located between devices requiring different insulation thicknesses may be unevenly etched during such processing. As a result, such STI regions are formed with uneven heights (or “step heights”).
Accordingly, it is desirable to provide methods for fabricating integrated circuits with isolation regions having uniform step heights. In addition, it is desirable to provide methods for fabricating integrated circuits with isolation regions having uniform step heights that require no additional masking steps. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.